1. Field of the Invention The present invention generally relates to integrated circuits, particularly those used with computer systems, and more particularly to an improved method of scanning high speed integrated circuits (including microprocessors) to test logic circuits and interconnections.
2. Description of Related Art
Integrated circuits are used in a wide variety of products, and many of these circuits, such as microprocessors, adapter chips, etc., have complicated logic designs. These designs are often buried in the microchip layers, and can be difficult to test. A generalized integrated circuit is shown in FIG. 1. Circuit 10 includes several logic function circuits 12, 14, 16 and 18, and several flip-flops, or latches, 20, 22, 24, 26 and 28. The logic functions have various inputs, and their outputs are connected to various latches, for example, logic function 12 has four outputs respectively connected to latches 20-26. Each logic function has many logic components (gates, inverters, etc.) arranged to provide a particular function, such as a register or execution unit. The latches store data, and may provide inputs to other logic functions, such as latches 20 and 24 which are connected to logic function 16. Circuit 10 may have one or more latches such as 28 which provides the output of the circuit. A clock signal 30 provides synchronization (control) for the latches. The clock may be a primary input to the circuit or internally generated.
Those skilled in the art will appreciate that, in the example of FIG. 1, the circuit is greatly simplified since there are many more logic functions and latches in a typical integrated circuit, and the logic functions can be very complicated; additionally, more than one clock signal can be provided. This figure is still adequate, however, for understanding how testing of the integrated circuit (or portions thereof) can be performed. One method involves the use of test patterns which are fed into the primary inputs of the integrated circuit while the output is examined. This approach is limited by the structure of the logic design and may fail to detect unusual flaws or defects in a particular design.
Another testing approach is to provide a mechanism for setting the latches to predefined states using special lines which are provided on the microchip, such as scan line 32 which is connected directly to latch 20, and scan line 34 which directly interconnects latch 20 with latch 28 (other scan lines, not shown, can be provided for the other latches, depending upon the type of scan implementation). Separate control is provided for scanning the latches, using a test clock 36. A scan output line 38 may also be provided. The relationship between the scan circuitry (tester) and the integrated circuit is thus master-slave, i.e., the tester is the master and controls the integrated circuit (the device under test, or DUT). As noted in the foregoing paragraph, while the scan design depicted in FIG. 1 is fairly simple, conventional scan designs can have greatly increased complexity according to the sophistication of the logic circuits and the desired testing capabilities. Scan functions typically provide a lower grade implementation than the full functionality afforded by the DUT.
Some testers (e.g., the multiplexed D flip-flop scan design) suffer from the disadvantage of not being able to scan the DUT at its intended operational speed (the "at-speed" defined by the integrated circuit's system clock). With reference to the example of FIG. 1, the clock speed of the system clock signal 30 would thus be significantly higher than the speed (frequency) of the tester clock signal 36. This limitation is generally applicable to high speed integrated circuits, that is, those running a system clock at greater than 100 MHz, and the effects are even more pronounced at speeds greater than 500 MHz, and still worse at state-of-the-art speeds of 1 GHz or more. The slower scan speed is required as a result of various physical constraints that arise between the tester and the chip, that are different from corresponding constraints that exist within the chip. Clock synchronization is difficult, and the slightest discontinuities in the wires between the tester and the chip can lead to considerable signal degradation. If a scan is run at a very high clock speed, logic errors may occur that do not accurately reflect the normal operation (non-scan mode) of the DUT.
A variation of this test technique, IBM's Level Sensitive Scan Design (LSSD) testing, can be adapted to provide at-speed testing of integrated circuits, by using a frequency multiplying device. See U.S. Pat. No. 5,614,838. At-speed testing is achieved even though the tester is not capable of generating the necessary signals at the frequency required by the DUT. This approach, however, has several disadvantages. The first disadvantage is the added complexity that is required for LSSD (as compared to a generalized scan design, or GSD, which does not use level sensitivity). Also, since the internal clock is derived from the tester clock by frequency multiplication, the design requires narrow tolerances on this tester clock and control signals so that the DUT can synchronize successfully. These tolerances are difficult to achieve for very high speed testing.
Other techniques can be used to provide at-speed testing, but they suffer other limitations. For example, at-speed testing can be achieved by decoupling the scan path interface, as taught by U.S. Pat. No. 5,381,420. The internal scan paths are driven by the system clock of the DUT, but the test logic is driven by the test clock. That design also uses a serial-to-parallel converter on the data input. As a consequence, even though the tester can perform a given scan of the DUT at full speed, new scan data is not provided at every cycle of the DUT. In U.S. Pat. No. 5,355,369, the DUT is required to have a digital processor that is functional enough to load from and store to a digital test register. This restriction is not too severe if the test is used to screen parts of a chip whose design is known to be functional, but it becomes impractical for testing of a new design. Another approach, discussed in U.S. Pat. No. 5,519,715, achieves at-speed testing operation by disabling the processor while slowly loading caches with test programs and data. This method cannot, however, operate a scan chain at high frequency, and does not allow high speed scan test (AC test) of single functional blocks within the processor.
In light of the foregoing, it would be desirable to devise a method of scanning an integrated circuit which allowed for at-speed testing, but did not impose excessive overhead on the latches by the scan chain. It would be further advantageous if the method could address additional problems that arise with scan paths, such as dealing with heavily loaded signals which must be amplified to desired levels and distributed over the chip, often via long wires in the scan path. Finally, to ensure that the scan test closely resembles actual high-speed operation, it is desirable to not change clock frequencies between scan and functional mode.